A multi-level ladder converter supporting vertically-stacked digital voltage domains

Modern digital systems are severely constrained by both battery life and operating temperatures, resulting in strict limits on total power consumption and power density. To continue to scale digital throughput at constant power density, there is a need for increasing parallelism and dynamic voltage/bias scaling. This work presents an architecture and power converter implementation providing efficient power-delivery for microprocessors and other high-performance digital circuits stacked in vertical voltage domains. A multi-level DC-DC converter interfaces between a fixed DC voltage and multiple 0.7 V to 1.4 V voltage domains stacked in series. The converter implements dynamic voltage scaling (DVS) with multi-objective digital control implemented in an on-board (embedded) digital control system. We present measured results demonstrating functional multi-core DVS and performance with moderate load current steps. The converter demonstrates the use of a two-phase interleaved powertrain with coupled inductors to achieve voltage and current ripple reduction for the stacked ladder-converter architecture.