An ASIC emulates the inner ear as a bank of 100 exponentially distributed asymmetric band-pass filters that roll off at up to 450dB/dec and have individually tunable Q-factors. The output is encoded into an auditory-nerve-like pulsed format on a digital port. The chip is integrated in a 0.5/spl mu/m process and consumes 2.6mW at 3.3V.
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Eric Fragnière (2005) studied this question.
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