A 20 ns battery-operated 16 Mb CMOS DRAM

An address-multiplexed 16-Mb CMOS DRAM (dynamic random-access memory) that has RAS access time of 20 ns at 3.3 V and 36 ns at 1.8 V is described. Three circuit techniques are employed: (1) parallel column access redundancy combined with a current sensing address comparator; (2) a gate isolated sense amplifier with low threshold voltage; and (3) a short signal path architecture with a layout for the LOC package. Access speed degradation is minimized even at 1.8 V Vcc. A table summarizing process and performance for the device is presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>