Pocket implant is widely used in deep-sub-micron CMOS technologies to combat short channel effects. It, however, brings anomalously large drain-induced threshold voltage shift and low output resistance to long channel devices. This creates a serious problem for high-performance analog circuits. In this paper, the first physical model of these effects is proposed and verified against data from a 0.18 /spl mu/m technology. This model is suitable for SPICE modeling.
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Cao et al. (2003) studied this question.
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