5D chiplet–interposer integration has emerged as a promising approach for building scalable many-core systems, where multiple chiplets communicate through a shared silicon interposer. In such architectures, chiplet–interposer interface selection directly affects traffic distribution and communication efficiency. However, the performance implications of different interface selection strategies remain insufficiently understood. This paper presents a systematic study of cross-chiplet interface selection as an independent design dimension in 2.5D chiplet–interposer networks. Three representative strategies are evaluated: Random Interface Selection (RIS), Hash-Based Interface Binding (HBIB), and Region-Aware Interface Selection (RAIS). Using the gem5/Garnet cycle-accurate simulation framework, we conduct extensive experiments under representative synthetic traffic patterns and analyze network latency, saturation throughput, routing path efficiency, and interface load distribution. Experimental results show that HBIB achieves superior and more stable performance by distributing traffic more evenly across boundary interfaces. RIS provides moderate and stable performance due to its probabilistic traffic distribution, whereas RAIS tends to concentrate traffic on a limited subset of interfaces under skewed workloads, resulting in load imbalance and earlier congestion. These findings highlight that balanced interface utilization is a key factor for efficient cross-chiplet communication in emerging chiplet-based systems.
Hou et al. (2026) studied this question.