Noise margin enhancement of Conventional 6T SRAM Cell by aspect Ratio Optimization

In proposed work, aspect ratio optimization of Conventional 6T SRAM cell transistors has been presented for improvement cell in stability using gpdk 90nm technology with Cadence virtuoso tool. Initially read and write stability has been investigated by varying cell ratio, pull-up ratio, temperature and supply voltage by using N-curve method. Optimized 6-T SRAM cell stability parameters for 1V supply voltage have been compared with NC-SRAM cell and 9T SRAM cell. A significant improvement of 33.15%, 78.14%, 21.63% and 61.82% is observed in static voltage noise margin(SVNM), static current noise margin(SINM), write trip voltage (WTV) and write trip current (WTI) metrics respectively as compared to NC-SRAM cell. Improvement in stability parameters is observed with rise in supply voltage whereas, with rise in temperature stability parameters deteriorates gradually.