An SRAM-Based Multi-Operand Architecture Implementing Multi-Bit Boolean Functions Using in-Memory Periphery Computing

This paper introduces a highly scalable in-memory computing architecture for implementing (1) <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</tex>-operand, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</tex>-bit Boolean functions, viz., AND/NAND/NOR/OR, (2) any arbitrary Boolean function expressed as the sum of products (e.g., F=AB'CD+ABC'D'), (3) <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</tex> parallel 2-bit XOR operations. Our technique performs operations using a modified 9T SRAM cell-based peripheral circuitry near the SRAM array. Unlike conventional 9T SRAM designs that use the same bitlines for both read and write operations, our design introduces dedicated read lines to separate the read and write paths. This separation improves efficiency and allows in-memory implementation of complex Boolean operations. To implement <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</tex> -operand, <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</tex> -bit AND/OR operations, the periphery circuit has <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</tex> compute blocks, each with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</tex> columns. The compute block stores the input operands along with configuration bits to choose the correct operation. An equality checker circuit compares the input operands with configuration bits to obtain original or complemented input. The outputs of equality checkers of different columns are connected to a product line, and by DeMorgan's theorem, either AND/NAND or NOR/OR can be realized. Using TSMC 65nm PDK in Cadence Virtuoso, we have demonstrated 64-bit AND/NAND/OR/NOR operations and 64 parallel 2-bit XOR operations. At 0.7V VDD, our design consumes 24.5fJ/bit and operates at 660MHz for XOR operations and 384MHz for other operations.