A memory cell capable of storing multilevel or analog information and providing random-access operation with nondestructive readout has been studied. It uses a single junction field-effect transistor (JFET) as the storage cell. Experimental and analytical studies suggest that eight of sixteen level operation should be feasible with refresh operations every 0.1 to 1 s; cell area can be under 2 mil/SUP 2/. Tracking voltage and current reference circuitry is used to accommodate variations in fabrication processing and operating temperature.
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Heald et al. (1976) studied this question.
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