A BiCMOS analog neural network with dynamically updated weights

A 64-neuron electrically trainable BiCMOS analog neuroprocessor based on three-layered PDP networks is described. The minimum feedforward propagation time is 10 mu s, equivalent to operation speed of 10/sup 8/ multiplications/s. Analog neuroprocessors with a storage capacitor for the synapse have been studied. The short retention time of the synapse weight has been an obstacle to the development of an analog neurochip. A dynamic refresh technique described here increases the retention time of the synapse weight, leading to a practical implementation of the neuroprocessor. The approach is to refresh the weight charge in the same manner as in DRAMs. All outputs from the synapses on the same column are summed and sent to a neuron cell. The weight from an off-chip digital memory is converted to analog form and then written on the storage capacitor of a synapse selected by x and y decoders. This scheme permits updating the weight by addressing the synapses sequentially. Iteration number in backpropagation learning depends on the operation accuracy of a sigmoid function generator and a multiplier. The network is hardly trained when the multiplier error is larger than 20%. To reduce the error, the neuroprocessor is based on a bipolar-MOS analog circuit, using bipolar transistors for both the multiplier and the sigmoid function generator.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>