Doubly twisted torus networks for VLSI processor arrays

The twisted torus processing surface, introduced and analyzed by Martin,1,2 is extended to contain a double twist and then mapped into a two-dimensional network suitable for implementation on a VLSI wafer. The result is a homogeneous, isotropic multiprocessor configuration without boundaries. Every processor has four nearest neighbors, and the interconnections between all pairs of processors are of approximately equal length. Special attention is given to mapping binary trees onto the processor array. Most divide-and-conquer-type problems will distribute themselves relatively uniformly over all available processors. Nine building blocks are introduced that will permit making doubly twisted torus arrays of arbitrary sizes.