A 34M transistor stream processor SoC for signal, image, and video processing contains 80 parallel integer ALUs organized into 16 data-parallel lanes with a 5-ALU VLIW per lane, two CPU cores and I/Os. Implemented in a 0.13mum CMOS technology, sixteen 800MHz data-parallel lanes combine to deliver performance of 512 8b GOPS or 256 16b GOPS.
No takes yet. Share an insight, caveat, or question.
Khailany et al. (2007) studied this question.
Synapse has enriched 4 closely related papers on similar clinical questions. Consider them for comparative context: