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Thin-film transistors (TFTs), e.g., based on organic semiconductors, oxides, perovskites, and two-dimensional materials (such as graphene or MoS2), are often fabricated without patterning a rectangular channel strip between the contacts, to keep the fabrication flow simple and the material pristine. However, this makes it difficult to extract current density and mobility due to fringing currents, which, if ignored, lead to overestimation of these device metrics. Furthermore, the extent of current spreading varies wildly from device to device depending on geometry, bias, as well as transport characteristics such as contact resistance and velocity saturation. We explore the impact of each of these factors through detailed simulations and discuss the subtle ways in which bias-dependent fringe currents can impact device characteristics. For TFTs where contact resistance and velocity saturation are negligible, we provide a simple analytical model that quantifies fringe currents with an error of ≤ 0.01% in common geometries. For unpatterned-channel TFTs with significant contact resistance or velocity saturation, our simulations reveal that either effect can more than double the fringe current. This can translate to the overestimation of current density and mobility by over 70%, even in devices with a contact width over 10× the channel length. If patterning the channel and using very wide contacts are impractical, proper device characterization thus necessitates correcting for fringe currents. By highlighting the utility of simulations and analytical models in this endeavor, this work provides insights into greatly assisting the rapid quantitative assessment of TFTs and intuition for identifying the intricate effects of current spreading on device characteristics.
Köroğlu et al. (Fri,) studied this question.