Architectural synthesis for digital neural networks

Using automated synthesis techniques, the design cycle of digital implementations of neural networks can be reduced and the design space can be reduced and the design space can be extensively searched. This will lead to the development of inexpensive commercial hardware for neural real time applications that satisfy response time and silicon area constraints. The authors present an automated architectural synthesis methodology for implementing digital neural networks. The synthesis approach and the trade-offs involved in the designs are presented. The synthesis is based on VLSI multiple-bus/functional unit architectures with internal parallelism. The functional units used in these architectures, their components, and features are discussed. Examples of various architectures for backpropagation and counterpropagation neural networks used in robotic and signal processing applications are also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>