Loopback architecture for wafer-level at-speed testing of embedded HyperTransportTM processor links

We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransporttrade (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin visibility. We demonstrate production screening of 45-nm SOI-CMOS wafers at 6.4 Gb/s.