Power benefit study for ultra-high density transistor-level monolithic 3D ICs

The nano-scale 3D interconnects available in monolithic 3D IC technology enable ultra-high density device integration at the individual transistor-level. In this paper we demonstrate the power benefits of transistor-level monolithic 3D designs. We first build a cell library that consists of 3D gates and model their timing/power characteristics. Next, we build timing-closed, full-chip GDSII layouts and perform sign-off iso-performance power comparisons with 2D IC designs. We also study the characteristics of benchmark circuits that maximize the power benefits in monolithic 3D designs. Lastly, our study is extended to predict the power benefits of monolithic 3D designs built with future devices.