The ultrareliable low-latency communication (URLLC) application scenario requires the adoption of short linear block codes to satisfy the low-latency requirements. Guessing random additive noise decoding (GRAND) is a prominent universal decoding solution for short linear block codes that lends itself to efficient hardware implementations. GRAND-based hardware implementations generally offer reduced average decoding latency but their high worst-case (W.C.) latency renders them unsuitable for deployment in mission-critical applications. This article presents an improved version of step-GRAND, a soft-input variant of GRAND that features a novel test error pattern (TEP) generating approach. A novel very large-scale integration (VLSI) architecture is developed for the execution of the improved step-GRAND algorithm with reduced W.C. decoding latency. Application specific integrated circuit (ASIC) implementation results, employing low-power (LP) TSMC 65-nm CMOS technology, demonstrate that the proposed improved step-GRAND can achieve an average decoding latency as low as 10 ns for decoding a <tex-math notation="LaTeX">$(128,105)$ </tex-math> linear block code at a target frame error rate (FER) of <tex-math notation="LaTeX">10⁻⁷ </tex-math>, while the W.C. decoding latency can reach <tex-math notation="LaTeX">300~ns~ 1~μ s </tex-math> depending on the parametric settings. Compared with the previously proposed baseline soft-input ordered reliability bits GRAND (ORBGRAND) hardware implementation with similar decoding performance at target FER of <tex-math notation="LaTeX">10⁻⁷ </tex-math>, the improved step-GRAND hardware achieves <tex-math notation="LaTeX">7 × ~ 17× </tex-math> reduction in W.C. latency, <tex-math notation="LaTeX">7× </tex-math> reduction in power consumption, and <tex-math notation="LaTeX">37 × ~ 66× </tex-math> higher area efficiency in the W.C. scenario. Furthermore, the proposed hardware can achieve an average throughput of up to 10.5 Gb/s and a W.C. throughput of <tex-math notation="LaTeX">102~ 350 </tex-math> Mb/s.
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Abbas et al. (2025) studied this question.