Hardware-Software Co-Design for Whitening using Zero-Phase Component Analysis

Zero-phase component analysis (ZCA) is a promising de-correlation technique in data pre-processing. It avoids stochastic axis swapping issues that prevailed in other preprocessing methods. ZCA evaluation of a signal has three major computational units such as (i) covariance matrix, (ii) eigenvalue decomposition and (iii) whitened matrix. Eigenvalue decomposition is an intensive computational unit in ZCA. In this paper, we implemented the ZCA algorithm on a PYNQ FPGA platform using HW-SW co-design framework to achieve hardware acceleration. Firstly, we implemented eigenvalue decomposition using Lanczos and implicit TriQR algorithm as a hardware IP and computed its hardware acceleration on PYNQ-Z1 FPGA. Secondly, we partitioned the ZCA algorithm as (i) covariance matrix and whitened matrix evaluation on processing unit and eigen decomposition unit on hardware IP, (ii) covariance matrix evaluation on processing unit and eigen decomposition unit along with the whitened matrix evaluation on hardware IP. The complete ZCA whitening system was designed using the AXI-Lite interface between the processor and hardware IP logic unit. The hardware acceleration factor and the resource utilization for ZCA whitening are reported for different input dimensions. The implementation results demonstrate that the HW-SW co-design attained hardware acceleration of 8x to 18x for varied input data feature dimensions between <tex>1000× 10</tex> and <tex>1000× 20</tex>.