TiON/NiO x Heterojunction Neuron for CMOS-Compatible Hardware Implementation of Activation Function in Neural Network

This study presents a compact neuron device based on a PN heterojunction neuron to enable hardware-level deep neural networks (HDNNs) with improved integration density beyond the limits of complementary metal-oxide-semiconductor (CMOS) neuron circuits. By systematically analyzing the energy-band structure, diode parameters, and dominant conduction mechanisms, the physical origin of the intrinsic thresholding behavior in the PN heterojunction neuron is identified. As a hardware neuron device, the PN heterojunction neuron exhibits rectification and nonlinear activation characteristics, while the threshold voltage (Vth) is 2.49 V and the rectification ratio (RR, ratio of current at ±3 V) is 104, allowing the direct implementation of the rectified linear unit (ReLU) function at the device level. The PN heterojunction neuron reliably receives and processes summed currents from synapse devices, demonstrating accurate ReLU operation, where linear signal transmission occurs only when the total synaptic conductance (Gtot) exceeds 110 nS, while no signal is transmitted below 110 nS. Furthermore, by integrating the PN heterojunction neuron with a commercial transistor, signal propagation across multiple layers is attained, confirming compatibility with multilayer HDNNs. Owing to its simple structure, intrinsic nonlinearity, and high scalability, the PN heterojunction neuron provides an effective solution to the area and complexity challenges of CMOS-based neuron implementations and exhibits strong potential for highly integrated and energy-efficient HDNNs.