Programmable Connections in Neuromorphic Grids

We describe asynchronous circuits that can relay spikes between multiple chips in a grid. These circuits interface with an on-chip SRAM to implement programmable connectivity among chips. We introduce a packet format that is compatible with updating the SRAM. From a high level specification, we synthesized and fabricated these circuits in an area of 0.206mm 2 in 0.18- μ m CMOS technology. Test results that measure performance and demonstrate correct function on first silicon are presented.