An image filtering processor for face/object recognition using merged/mixed analog-digital architecture

This paper proposes an image-filtering processor LSI based on a hybrid approach using pulse-width modulation (PWM) and digital circuits. The LSI has been designed for implementing convolutional neural networks with a very large convolution-kernel size. The LSI designed using a 0.35 /spl mu/m CMOS performs 6-bit precision convolutions for an image of 80/spl times/80 pixels with a kernel size of up to 51/spl times/51 pixels within 8.2 ms. All operations for the fabricated LSI have been successfully verified. The power consumption estimated from SPICE simulation is 280 mW.