Design tradeoffs in stall-control circuits for 600 MHz instruction queues

A 600 MHz superscalar Alpha microprocessor contains separate integer and floating-point issue units. The integer issue unit selects up to four data-ready instructions to issue out of a 20-entry queue. The floating-point issue unit, similarly, selects two instructions out of a separate 15-entry queue. Though their operation is similar, the two queues required different tradeoffs to meet design goals. This paper first describes functions common to both queues, then discusses specific tradeoffs made in the implementation of each queue's stall control circuits.