A dual-core 64b Xeonreg MP processor is implemented in a 65nm 8M process. The 435mm 2 die has 1.328B transistors. Each core has two threads and a unified 1MB L2 cache. The 16MB unified, 16-way set-associative L3 cache implements both sleep and shut-off leakage reduction modes
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Rusu et al. (2006) studied this question.