Design and optimization of 5 × 5 Network on the securing router with integrated SHA-3 & AES core in FPGA for wearable applications

Network-on-Chip (NoC) has been a scalable and effective communication platform for contemporary multi-core systems, providing high-speed data exchange among IP cores with optimized power usage and security. Conventional NoC designs are plagued by latency bottlenecks and security issues, especially in wearable devices, where low power, real-time processing, and data confidentiality are essential. The current work introduces a 5 × 5 NoC router designed specifically for secure, low-power wearable systems, that employs AES-128 encryption and SHA-3 hashing to achieve end-to-end data integrity and confidentiality. Cryptographic cores are provided at the NI level based on pipeline-based encryption to minimize the processing overhead. The suggested FPGA-based NoC design reduces the utilization of logic gates by 10%, increases the speed of data processing by 5%, and decreases power consumption by 20%, which is suitable for resource-limited situations. Performance measurement under mixed traffic loads reveals that at a 1 Gbps injection rate, the system supports an end-to-end aggregate throughput of 1.05 Gbps with reduced flit transmission latency by 25% (from 120 to 90 ns) over traditional NoCs. The system also provides improved security with minimal degradation in throughput and a balance among data protection, performance, and power efficiency. These optimizations make the suggested secure NoC a strong candidate to implement real-time, low-power applications in wearable and IoT settings.