A Number System Approach for Adder Topologies

The design space exploration for fast and power efficient adders is of increasing interest for microprocessors and graphic and digital signal processors. Recently, several methods have been proposed to explore the design space of adders, where well known designs appear as possible instances. These methods are based on the identification of parameters that lead to different hardware structures. In this work, we go a step further by exploring the mathematical foundation behind the trees for carry computation. We propose an algorithm that allows to obtain any adder topology based on design decisions. The method is based on finding representations of integers in a given number system. This leads to an adder model that allows the design of any adder structure in a compact a formal way. The proposed formal model might be useful for a formal design description of adders and it can be incorporated to CAD tools.