A 64b integer execution ALU is described for 4GHz single-cycle operation with a 32b mode ALU latency of 7GHz. The 0.073mm/sup 2/ chip is fabricated in a 90nm dual-V, CMOS technology and dissipates 300mW. Sparse-tree adder architecture, single-rail dynamic circuits, and a semidynamic implementation enable a 20% performance improvement and a 56% energy reduction compared to a Kogge-Stone implementation.
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Mathew et al. (2004) studied this question.
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