An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-Chip

We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out