Development and Evaluation of an Educational Environment for Designing Hardware Architectures of Support Vector Machines‐Based Classifiers

ABSTRACT In an increasingly complex world where increased interactions between users and systems are taking place and a greater amount of information must be processed, Machine Learning techniques are becoming increasingly relevant as they help researchers to generalize how the different variables in a process are related and, consequently, reduce the margin of error in the estimation of results. One of these techniques is Support Vector Machines (SVM), which are characterized for being simple, flexible, and computationally efficient. They are also useful for classifying and analyzing data for regression tasks in multiple areas such as natural language processing, image classification, bioinformatics, signal processing, as well as robotic systems. In this regard, several current studies have optimized performance and cost by implementing SVM in hardware, particularly on Field‐Programmable Gate Array (FPGA) as they are suitable for dealing with challenging embedded system constraints. Consequently, undergraduates must be familiarized with this approach to be more competitive when entering the labor market in the real industry. Therefore, it is imperative to create teaching alternatives that provide practical knowledge about SVM, not only from a software perspective, but also on the design and modeling of hardware architectures that describe their structure and can be implemented in a specific device. With this aim in mind, this study presents a learning‐by‐doing educational approach for teaching the principles of SVM by promoting their modeling, implementation, and evaluation on FPGAs. Furthermore, the results derived from an empirical evaluation on 55 undergraduates from the Universidad Tecnológica de la Mixteca, México, provided evidence that the proposed approach can stimulate the development of skills required in the labor market related to the design and modeling of hardware architectures and, at the same time, allows students to undertake design challenges involving SVM and reconfigurable logic.