Test Scheduling of Core Based System-on-Chip Using Modified Ant Colony Optimization

A System-on-Chip (SoC) is an integrated circuit that combines various electronic components in a single die. The SoC components mostly involve user-defined logic, embedded memories, analog, digital and mixed-signal blocks. The testing of an SoC for manufacturing defects is an important task due to IC design complexity, further, it also affects the final cost of the chip. Due to the high complexity involved in SoC test scheduling, various techniques were suggested to reduce the testing time. This paper introduces a novel SoC test scheduling technique based on a Modified Ant Colony Optimization (MACO) algorithm. The testing is performed on the benchmark circuits of ITC'02. The experiments performed on d695 and p22810 SoC benchmark circuits. The results show that the MACO algorithm can achieve reduced test time compared to the ACO algorithm. When compared with ACO, the proposed algorithm MACO reduces the testing time by 47% and 10% for d695 and p22810 SoC benchmark circuits respectively.