A study of interleaved memory systems

There is frequently a severe mismatch between achievable processor and memory speeds in today's computer systems. For example, the CDC-7600 has a 27ns (nanosecond) processor cycle time and a 270ns memory cycle time; the IBM-360/91 has a 60ns processor cycle time and a 750 ns memory cycle time. In order to obtain the desired increase in the effective memory speed, an efficient memory system must use such techniques as interleaving memory modules and implementing an automatic level in a memory hierarchy (e.g., a slave memory as in the IBM-360/85 or 195 and the CDC-7600). In the past, interleaving was often studied by simulation using a random address generating source to obtain memory requests. This paper discusses results of mathematical analyses of models of interleaved memory systems. In these investigations the properties of addresses generated by instructions and data have been distinguished.