Design of RM-nc: a reconfigurable neurocomputer for massively parallel-pipelined computations

The design of RM-nc, a reconfigurable machine for massively parallel-pipelined computations, is considered with the objective of demonstrating that a completely reconfigurable platform, not only in the domain of communication and control but also in the domain of processing elements (PEs), is feasible. The implementation of a fast computational element and control environment for neural network simulations is presented in order to assess the cost of providing reconfigurability at computational level. The implementation of a fast floating-point sum-of-products circuit using special carry-save multipliers and extensive pipelining is outlined on a field programmable gate array (FPGA) platform. It is shown that the flexibility of FPGA devices can contribute to achieving good time/hardware performance when far less complex neurons are sufficient for simulation of a given neural network model.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>