High-accuracy MOS models for computer-aided design

This paper presents accurate device models (1-3 percent) to describe the <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ID-VD</tex> electrical characteristics of surface-channel PMOS transistors in strong inversion, and ion-implanted depletion-mode buried-channel PMOS transistors. The primary emphasis is an accurate description of the transverse carrier mobility with distance and normal electrical field in long-channel structures. The influence of substrate bias on carrier mobility in the surface-channel device is modeled theoretically and verified by experiment. The carrier mobility in the buried-channel devices is constant as determined experimentally with gated-diode <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C-V</tex> and conductance measurements. The modeling parameters are determined at <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD = 0</tex> with an automated data-acquisition micro-processor-controlled system. The models are analyzed with a least squares estimation criterion and a high degree of internal consistency is apparent from the statistical significance of the results.