A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation

A subthreshold ECG processor in IBM 45 nm SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (E min ) at the MEOP. SEC is shown to reduce E min by 28% compared to the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% pre-correction error rate p e . These results represent an improvement of 19× in beat-detection performance, and 600× in p e over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state-of-the-art while tolerating 16× more voltage variations.