A Sub-Microwatt Class-AB Super Buffer: Frequency Compensation for Settling-Time Improvement

This brief presents a frequency compensation technique to improve the settling time in driving moderate capacitive load (10-20 pF) of a low-power (<;1 μW) class-AB super buffer, wherein previously reported super buffers exhibit poor stability performance. From post-layout simulations in a 0.18-μm CMOS process, the proposed super buffer-while driving a 10-pF load and consuming less than 1 μA of quiescent current from a 1.2-V supply voltage-achieves a factor of 1.8 (positive output direction) and 5.1 (negative output direction) reduction in the settling time compared to before compensation. We also validated the proposed technique through the measurements of a super buffer built on a protoboard with commercial discrete MOS transistors.