This paper presents an optimized column FFT architecture which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, the system can compute a 24-bit precision 1 K point complex FFT transform within 9.25 /spl mu/s, far surpassing the performance of any existing FFT systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Sunada et al. (2002) studied this question.
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