A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM's

This paper proposes and reports a low-power SRAM using a charge-transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier overcomes the V/sub th/ relative difference between the pair MOS transistors, and thus reduces the input offset voltage. The encoded-bus scheme reduces the number of signals being switched to cut the capacitive load. These read-path dynamic circuits have eight-timings which a low-power DLL produces. The fabricated 0.35-/spl mu/m-rule 2k-by-16-bit SRAM operated at 50 MHz with the power dissipation of 5 mW at 1 V.