A CAD manufacturability analysis environment, MAPEX, is described in this paper. It can be used to extract a large number of manufacturability/yield relevant design attributes from an IC layout. The extracted attributes can then be used to improve design tools/strategies or to analyze the reasons for observed yield loss.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Heineken et al. (2002) studied this question.
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