This paper analyzes the step load response of a current-mode-controlled pulsewidth modulation (PWM) converter and also presents design guidelines for obtaining a good step load response. Analytical expressions for the step load response are derived in terms of the power stage and feedback compensation parameters. Control design to minimize the overshoot and settling time of the output voltage is presented. Analysis results are verified by large-signal simulations.
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Byungcho Choi (1997) studied this question.
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