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We illustrate a new method to characterize the energy dissipation of circuits by collapsing closely related input transition vectors and energy patterns into capacitive coecients. Energy characterization needs to be done only once for each module (ALU, multiplier etc.,) in order to build a library of these capacitive coecients. A direct high-level energy simulator or proler can then use the library of pre-characterized modules and a sequence of input vectors to compute the total energy dissipation. A heuristic algorithm which performs energy clustering under objective constraints has been devised. The worst case running time of this algorithm is O(m 3 n), where m is the number of simulation points and n is the number of inputs of the circuit. The designer can experiment with the criterion function by setting the appropriate relative error norms to control the `goodness' of the clustering algorithm and the sampling error and condence level to maintain the suciency of representation of each cluster. Experiments on circuits show a signicant reduction of the energy table size under a specied criterion function, cluster sampling error and condence level.
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Mehta et al. (1996) studied this question.