Memristive devices based on vertical heterostructures of graphene and TiOx show a significant power reduction that is up to ∼103 times smaller than that of conventional structures. This power reduction arises as a result of a tunneling barrier at the interface. The barrier is tunable, opening up the possibility of engineering several key memory characteristics. As a service to our authors and readers, this journal provides supporting information supplied by the authors. Such materials are peer reviewed and may be re-organized for online delivery, but are not copy-edited or typeset. Technical support issues arising from supporting information (other than missing files) should be addressed to the authors. Please note: The publisher is not responsible for the content or functionality of any supporting information supplied by the authors. Any queries (other than missing content) should be directed to the corresponding author for the article.
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Qian et al. (2014) studied this question.
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