Effects of substrate resistance on CMOS latchup holding voltages

We suggest a method to estimate the effects of substrate resistances on the latchup holding voltage of CMOS integrated circuits. The estimated holding voltages are shown to be in reasonable agreement with the experimental data inspite of two bold approximations. Using this method, we analyze the effect of several variables relating to the epitaxial substrate and/or the well-isolation trench on the latchup holding voltage. It is shown that there may exist a certain optimum epitaxial layer thickness that leads to a maximum latchup holding voltage and that even a shallow trench is remarkably effective in raising the holding voltage. Physical explanations are offered for the effects of the epitaxial layer and trench on the holding voltage. Examples are presented to illustrate the general effects of several design variables and to aid the design and interpretation of process experiments.