Architectural-level error-tolerant techniques for low supply voltage cache operation

Supply voltage (V CC ) scaling is the most effective technique for reducing the energy consumption of microprocessors. Since V CC scaling increases the impact of parameter variations on circuit performance and functionality, circuits eventually fall out of specification, thus limiting the minimum operating supply voltage (V CCMIN ) for the microprocessor. The last-level cache (LLC) often determines V CCMIN . To maximize cache capacity, the LLC memory cell consists of near minimum-sized transistors, which are highly sensitive to process variations. For a tradition LLC, a small fraction of memory cells with large variations limit the V CCMIN for the entire microprocessor. In this paper, error-tolerant techniques dynamically reconfigure the cache to either disable or correct these failing memory cells to enable a lower V CCMIN at the cost of lower cache capacity, thus enhancing the microprocessor energy efficiency. At the high-V CC operating mode, the cache operates at full capacity to satisfy the high-performance target. At the low-V CC operating mode, energy consumption is the primary concern, and the cache is dynamically reconfigured with lower capacity to mitigate the impact of the failing memory cells on reliability. Since the clock frequency significantly reduces for the low-V CC mode as compared to the high-V CC mode, the reduction in cache capacity has a smaller effect on performance. In comparison to a traditional LLC design, simulation results indicate that the error-tolerant cache techniques decrease V CCMIN by 13-28%, corresponding to a 20-42% reduction in energy per instruction. Adding these techniques only incurs a 5-10% performance penalty at the low-V CC operating mode in comparison with a hypothetical idea cache.