A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration

We report an 11-b 20-Ms/s pipelined ADC in 0.18-μm CMOS with a novel dual-mode-based digital background calibration method that altogether corrects errors caused by gain insufficiency, gain nonlinearity, and capacitor mismatches. The calibration enables an intentional use of low-gain single-stage op amps instead of conventional high-gain multi-stage op amps, with which we achieve a total ADC power dissipation of 2.9 mW and a short convergence time of 10 5 . The calibration improves the SNDR from 45 dB to 60 dB, and the SFDR from 50 dB to 86 dB. The figure-of-merit is 174 fJ/conversion-step.