Novel Local Silicon-Gate Carbon Nanotube Transistors Combining Silicon-on-Insulator Technology for Integration

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> By taking advantage of the silicon-on-insulator technology and the <emphasis emphasistype="italic">in situ</emphasis> carbon nanotube (CNT) growth, new local silicon-gate carbon nanotube FETs (CNFETs) have been implemented in this paper. We propose an approach to integrate the CNFET onto the silicon CMOS platform for the first time. Individual device operation, batch fabrication, low parasitic capacitance, and better compatibility to the CMOS process were realized. The characteristics of the CNFETs are comparable to the state-of-the-art devices reported. The scaling effect, ambipolar conductance, Schottky barrier effect, and I–V characteristics noise were analyzed. The physical properties of the CNTs were also characterized. </para>