A unified hardware architecture that can be reconfigured to calculate 2, 3, 4, 5, or 7‐point DFTs is presented. The architecture is based on the Winograd Fourier transform algorithm and the complexity is equal to a 7‐point DFT in terms of adders/subtractors and multipliers plus only seven multiplexers introduced to enable reconfigurability. The processing element finds potential use in memory‐based FFTs, where non‐power‐of‐two sizes are required such as in DMB‐T.
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Qureshi et al. (2013) studied this question.