Memory Access Patterns for the Analysis of MPSoCs

Unlike distributed systems, multiprocessor systems-on-chip often cannot integrate all memory needed for high performance applications within each processor. Hence, accesses to instruction and data memory use the same communication infrastructure as communication between processes. In this paper, we give an overview on an approach to analyze system timing in the presence of memory and coprocessor accesses in MpSoC systems and present a method to derive safe bounds on the traffic generated by tasks as well as resources with multiple tasks mapped to it