A 10T SRAM Cell with Enhanced Read Sensing Margin and Weak NMOS Keeper for Large Signal Sensing to Improve VDDMIN

One read-write 8T SRAM cell with decoupled read port suffer data-dependent read bit line leakage, limiting VDDMIN of SRAMs in deep submicron technologies. This paper proposes a 10T SRAM cell in a typical sub-10nm FinFET technology with data-independent RBL leakage and enhanced RBL sensing margin: both voltage and time window to improve VDDMIN. 10T SRAM cell data-independent RBL leakage is improved by 15% compared to conventional 8T SRAM cell. At VDD=0.3V, our proposed 10T SRAM cell show significant RBL sensing voltage improvement of 155mV (~8.2x) compared to 19mV in conventional 8T SRAM. We also proposed a weak NMOS keeper to improve VDDMIN and Read `0' delay for large signal RBL sensing vs. conventional weak PMOS keeper. Our proposed weak NMOS keeper with NFIN=2 and NFIN=3 improves VDDMIN by 50mV and 90mV respectively against conventional PMOS keeper. Read `0' delay also improved for our proposed weak NMOS keeper with NFIN=2 and NFIN=3 against conventional weak PMOS keeper (0.15× at VDD=0.5V).