Energy efficiency deterioration by variability in SRAM and circuit techniques for energy saving without voltage reduction

The transistor variability deteriorates the energy consumption in SRAM. Especially it increases the energy consumed at the bitlines, which is the major portion of the total energy. The influence of the variation is enhanced at lower supply voltage, thus the voltage reduction sometimes degrades the energy efficiency. In this paper, we present circuit techniques that can reduce the SRAM energy consumption without the supply voltage scaling. An energy-efficient hierarchical bitline scheme can save energy consumption used for the bitline precharge. An energy-efficient offset-cancelling circuit and a process-variability-robust timing-generating circuit are also proposed.