A pseudo-random testing scheme for analog integrated circuits using artificial neural network model-based observers

This paper presents a simple and very efficient testing strategy for fault diagnosis of analog integrated circuits. The methodology is based on a technique of using a pseudorandom noise as the test pattern and a model-based observer for fast and robust testing and fault diagnosis. By incorporating device-level faults the efficiency is illustrated for stand-alone as well as embedded operational amplifiers as examples. The simulation results obtained are very encouraging. The technique can be viewed as a built-in self-test along with a design for testability scheme that dramatically improves the fault coverage and can be implemented for both on-line and off-line depending on the need of the application and silicon area overhead. Its main advantages are: a universal input stimulus (white noise) is used and thus test generation can be avoided, good and faulty signatures for high quality testing can be easily constructed and testing cost can be minimized, the technique is very efficient and robust, and the scheme can be well suited for built-in self-test implementation.