Power electronic applications come along with very high requirements in terms of reliability. Thermal loadings stress whole electronic packages while powering the semiconductor and by environmental temperature changes. Direct copper bonding (DCB) substrates are widely used in electronic applications due to its high thermal conductivity performance. They consists of copper layers sintered onto an Al 2 O 3 -ceramic sheet. Because of the very high process temperature, thermal inducted stresses arise along the substrate while cooling to ambient temperatures. The DCB substrates carry residual stresses usually which are concentrated along the edges of copper structures. Under service condition or even during the electronic manufacturing process the stress concentration might increase and in consequence copper structure rip off the substrate by cracking and conchoidal fractures in the ceramic sheet. To avoid the critical cracking situation the knowledge about the residual stress condition is required. The target will be a stress mapping across the DCB substrate. Within the paper one potential approach to measure the stress condition will be presented.
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Muench et al. (2017) studied this question.
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