Exploring the use of parallel prefix adder topologies into approximate adder circuits

Approximate adders are usually composed of two parts, i.e., the imprecise (approximate) part, which is a set of the least significant bits, and a precise part, with the remaining most significant bits. Previous works have exploited only the ripple carry adder (RCA) in the precise part of approximate adders. This paper proposes the exploration of different Parallel-Prefix adders (PPA) topologies in the precise part of approximate adders targeting the optimal combination between performance and power dissipation. Besides the RCA, we evaluate the use of Brent-Kung, Kogge-Stone, Han Carlson, Ladner-Fisher, and Sklansky PPAs in the precise part of two well-known approximate adders, i.e., Error Tolerant Adder I (ETA-I) and Copy adder. The adders were described in VHDL and synthesized to 45 nm CMOS technology. Results for 16-bit, 24-bit, and 32-bit approximate adders show that the PPA adders can improve clock frequency up to 2.22 times with a maximum energy consumption overhead of 7.4%.